systemverilog soft constraint
1.
class my_item; rand bit constrainted_random; rand bit usually_one; endclass class my_generator; my_item item; function void go(); item = new(); item.usually_one.rand_mode(0); item.usually_one = 1; for(int i = 0; i < 10; i++) begin assert(item.randomize() with {constrainted_random == bit'(i);}); $display("item=%0p", item); end item.usually_one.rand_mode(1); for(int i = 0; i < 10; i++) begin assert(item.randomize() with {constrainted_random == bit'(i);}); $display("item=%0p", item); end endfunction endclass module top(); my_generator generator; initial begin generator = new(); generator.go(); end endmodule
2.
class my_item;
rand bit constrainted_random;
rand bit usually_one;
function void pre_randomize();
usually_one = 1;
endfunction
endclass
class my_generator;
my_item item;
function void go();
item = new();
for(int j = 0; j < 2; j++) begin
item.usually_one.rand_mode(0);
for(int i = 0; i < 3; i++) begin
assert(item.randomize()
with {constrainted_random == bit'(i);});
$display("item=%0p (usually_one.rand_mode off)", item);
end
item.usually_one.rand_mode(1);
for(int i = 0; i < 3; i++) begin
assert(item.randomize()
with {constrainted_random == bit'(i);});
$display("item=%0p (usually_one.rand_mode on)", item);
end
end
endfunction
endclass
module top();
my_generator generator;
initial begin
generator = new();
generator.go();
end
endmodule
3.
soft my_arr inside {[1:6]};
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